
产品特点
01 312.500 MHz fundamental-mode operation
02 LVPECL output at 3.3 V
03 ±20 ppm frequency stability
04 35 fs RMS phase jitter (typ.)
技术规格
| 型号 | YN6312M500332015P |
|---|---|
| Package size | 2.0 × 1.6 mm |
| Output type | LVPECL |
| 电源电压 | 3.3 V |
| 频率范围 | 312.500 MHz |
| 振荡模式 | Fundamental |
| 频率稳定度 | ±20 ppm |
| 频率稳定度条件 | 包含初始频率公差, temperature variation, supply voltage change and 10 years aging (+25 °C) |
| 工作温度范围 | -40 °C to +105 °C |
| 储存温度范围 | -55 °C to +125 °C |
| 高电平输出电压 | VDD - 1.1 V min. |
| Low-level output voltage | VDD - 1.5 V max. |
| 电流消耗 | 60 mA max.; RL = 50 Ω to VDD - 2 V |
| Rise time | 0.4 ns |
| Fall time | 0.4 ns |
| Rise/fall measurement | Between 20% and 80% of (VOH - VOL) |
| Symmetry | 45% to 55% |
| Differential swing | 0.8 V to 2.0 V |
| 启动时间 | 10 ms; t = 0 at 90% VCC |
| 输出负载 | 50 Ω; terminated to VCC - 2.0 V |
| Tri-State - Output Enable | 70% VDD min. |
| Tri-State - Output Disable | 30% VDD max. |
| 三态控制条件 | OE为逻辑1时输出使能 or open; OE为逻辑0时输出禁用 |
| RMS phase jitter | 35 fs typ.; integrated from 12 kHz to 20 MHz at 312.5 MHz, 3.3 V |
原始规格书预览
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